Designing the implementation of AES on FPGA platforms

This work is addressed to those interested in the hardware implementation, using FPGA platforms (English Field Programmable Gate Array), of current cryptographic algorithms, whether they are students, masters, PhD students, teachers, researchers or enthusiasts of the field. It is an attempt to bring closer to this subject anyone who tries to design an application of this kind, assuming minimal knowledge of digital electronics, VHDL programming language (very high speed integrated circuit hardware description language), but also of cryptology.

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